A phase change memory, as typical of a memory with a programmable resistor element, is a non-volatile memory taking advantage of characteristics e.g. of a chalcogenide material, such as Ge, Sb or Te that, when the chalcogenide material is heated, it takes on an amorphous state (high resistance)/crystalline state (low resistance). In general, the material undergoes a transition between the high resistance (reset) state and the low resistance (set) state, by the Joule's heat, generated by the electric current, depending on the time duration of current application.
In a phase change memory, the write time on the order of tens to about one hundred nanoseconds is said to be necessary. The number of times of repeated write operations is on the order of 1012, which is of the same order of magnitude as that of the FLASH memory (electrically programmable erasable non-volatile memory) and lower by about four orders of magnitude than that of the DRAM (dynamic random access memory).
With the phase change memory, there is a possibility that device characteristics are deteriorated to destruct stored data with increase in the number of times of repetition of read/write operations.
As a method for improving disturbance and retention characteristic of the above-described memory with a programmable resistor element, several proposals have been made in e.g. Patent Document 1 (U.S. Pat. No. 6,646,902B2) and Patent Document 2 (U.S. Pat. No. 6,560,155B1). An example disclosed in Patent Document 1 (U.S. Pat. No. 6,646,902B2) is now briefly described with reference to FIG. 11. The programmable resistor element, used in this technique, is of a structure comprised of a silver (Ag) containing solid electrolyte 1103, as an example, sandwiched between an upper electrode 1101 and a lower electrode 1102. When the potential is applied across the electrodes, Ag+ ions are generated on ionization and combined with electrons to yield metal Ag which is precipitated to interconnect the upper electrode 1101 and the lower electrode 1102 to establish a low resistance state. When the reverse potential is applied across the electrodes, the precipitated Ag metals are caused to disappear to establish the high resistance state. This method provides for variable resistance value across the electrodes.
With the structure of FIG. 11, the possible retention time of the programmed state is on the order of hours or days. Although the retention time is longer than with the DRAM, the retention characteristic is inferior as compared to that of the normal FLASH memory. With this in view, a proposal is made for applying a voltage V2 which would not cause disturbances as compared to the voltage VI at the time of programming (about 35 to 60% of VI) for improving the retention characteristic.
In the Patent Document 2 (U.S. Pat. No. 6,560,155B1), it is proposed to carry out a refreshing operation for presenting a DRAM interface compatible memory employing a memory cell similar to one shown in Patent Document 1 (U.S. Pat. No. 6,646,902B2).
It is proposed that, since the retention characteristic of the memory cell with a programmable resistor element is superior to that of the DRAM, the inner refresh timing of a DRAM is delayed by a delay circuit, and a voltage is periodically applied to improve retention characteristic as well as to reduce the refresh current and power.
Although the phase change device is a non-volatile memory device, the resistance value thereof is changed by the voltage and the current applied to the device by read disturbances to cause a change in the resistance value of the phase change device to deteriorate the retention characteristic and the read margin.
It has also been recognized that, during writing, the change in the resistance value is deteriorated in similar manner with time, as a result of application of the voltage and the current to the phase change device, due to disturbances similar to the read disturbances, as shown in FIG. 9. In this figure, showing a change in the resistance value of the phase change device during write and read, the abscissa and the ordinate denote the number of read/write times and the set/reset resistance value of the phase change device, respectively.    [Patent Document 1] U.S. Pat. No. 6,646,902 (U.S. Pat. No. 6,646,902B2)    [Patent Document 2] U.S. Pat. No. 6,560,155 (U.S. Pat. No. 6,560,155B1)